A transmission and reception system for transmitting and receiving data signals often uses a clock signal to determine a transmission clock and a reception clock. In a transmission and reception system, such as Camera Link (Registered Trademark), in which a cycle of a clock signal is not identical to those of a transmission clock and a reception clock, a transmitter and a receiver use respective PLL (Phase Locked Loop) circuits so as to generate a transmission clock from a clock signal or so as to generate a clock signal from a reception clock. For example, in the Camera Link, a PLL circuit of a transmitter generates a transmission clock whose cycle is 2/7 times as long as that of a clock signal (whose frequency is 7/2 times as high as that of the clock signal). The transmitter transmits data at every rising edge of and at every falling edge of the transmission clock. In the Camera Link, a receiver reproduces, from a data signal which the receiver has received, a reception clock whose cycle is identical to that of the transmission clock. A PLL circuit of the receiver restores, from the reception clock, a clock signal whose cycle is 7/2 times as long as that of the reception clock (whose frequency is 2/7 times as high as that of the reception clock).
A PLL circuit typically has limitation on its operation band. Therefore, in a case where a bandwidth of a signal which a PLL circuit receives is large, a plurality of PLL circuits having respective different operation bands are prepared, and one of the plurality of PLL circuits which is to be used is selected in accordance with a frequency of the signal which the PLL circuit receives. The PLL circuit to be used is selected on the basis of a LOCK signal (which becomes active while the PLL circuit is stably operating) of the PLL circuit. On the other hand, the PLL circuit sometimes maintains a LOCK state in response to an input signal that exceeds a predetermined operation band. That is, it is difficult to correctly determine, from a state of a LOCK signal, whether or not the PLL circuit is properly operating.
In a case where the PLL circuit maintains the LOCK state in response to the input signal that exceeds the predetermined operation band, it is necessary to cause the PLL circuit to stably operate by resetting an operation of the PLL circuit. An example of a method of resetting the operation of the PLL circuit is a method of resetting the PLL circuit of the transmitter which resetting is triggered when the PLL circuit of the receiver is not in a LOCK state (i.e., an input signal exceeding the predetermined operation band is inputted). However, there is a possibility that the PLL circuit of the receiver is not optimized like the PLL circuit of the transmitter. That is, a case can be caused in which an operation band of the PLL circuit of the transmitter is inconsistent with that of the PLL circuit of the receiver (the PLL circuit of the transmitter and the PLL circuit of the receiver operate within respective different operation bands). Other examples of the method of resetting the operation of the PLL circuit are described in Patent Literatures 1 and 2 as below.
Patent Literature 1 describes a PLL circuit which, when a control electric potential of a voltage control oscillator circuit (VCO) reaches a predetermined upper limit or lower limit, automatically adjusts the number of stages of a ring oscillator to an optimal number of stages so that an output of the VCO has a desired frequency. The invention described in Patent Literature 1 makes it possible to reduce gain of the VCO even in a case where a variable frequency band is large. This allows the PLL circuit to be resistant to external noise.
Patent Literature 2 describes a clock circuit including (i) a clock comparator circuit which compares a constant frequency with a clock signal supplied from an input buffer, (ii) a multiplication setting circuit which sets a multiplication of a PLL on the basis of a multiplication selection signal, and (iii) a multiplication and frequency division setting circuit which sets a multiplication value of the PLL and a frequency division value of a frequency divider circuit on the basis of a multiplication and frequency division setting signal supplied from the multiplication setting circuit. The invention described in Patent Literature 2 makes it possible to automatically set a multiplication in accordance with a frequency of a bus without externally setting the multiplication.